The present invention relates to a semiconductor device constituted by a semiconductor chip having a protective wiring layer on an integrated circuit.
In recent years, electrically erasable programmable read only memories (EEPROMS) are being used as external memory devices in portable computers giving importance to communication functions.
A basic cell of a conventional EEPROM has a structure shown in FIG. 4. Referring to FIG. 4, a source 303 and a drain 304 are formed at a predetermined interval in a region defined by a field oxide film 302 on a p-type semiconductor substrate 301. A floating gate 306 electrically insulated from surroundings is formed through a gate insulating film 305 on the semiconductor substrate 301 and the drain 304 between the source 303 and the drain 304. A control gate 308 is formed on the floating gate 306 through an insulating film 307. The floating gate 306 and the control gate 308 are made of heavily doped polysilicon. Reference numeral 309 denotes an insulating film formed on the field oxide film 302 and the control gate 308.
In the above structure, part of the gate insulating film 305 between the floating gate 306 and the drain 304 is formed as thin as about 10 nm. In a data erase, when the control gate 308 is applied with a positive voltage much higher than a voltage to the drain 304, electrons enter the floating gate 306 from the drain 304. In a data write, by changing the polarity of the voltage applied to the control gate 108, the electrons within the floating gate 306 are removed to the drain 304. The electron flow passes through the thin gate insulating film 305 by a tunnel phenomenon.
When the floating gate 306 contains no electron, the transistor is turned on; when the floating gate 306 contains many electrons, a channel is hardly induced between the source 303 and the drain 304 by negative charges of electrons within the floating gate 306, and the transistor is not turned on. The two, ON and OFF states of the transistor correspond to data "0" and "1", respectively.
As described above, the EEPROM is advantageous in that data can be electrically written/erased in/from individual memory cells. However, data stored in the EEPROM is naturally erased by irradiation of ultraviolet rays.
For this reason, as disclosed in Japanese Utility Model Laid-Open No. 5-38915, a light-shielding film is conventionally formed on an EEPROM cell to shield the entrance of ultraviolet rays which causes a data erase. FIG. 5 shows a semiconductor chip having such a light-shielding film. An ultraviolet-shielding layer 403 is formed every memory cell in the region of an EEPROM 402 on a semiconductor chip 401 on which an integrated circuit is formed.
In the conventional semiconductor device, the ultraviolet-shielding layer 403 is only formed in the region of the EEPROM 402. If the ultraviolet-shielding layer 403 is damaged due to any reason, the damage to the layer 403 is not recognized until it is externally observed. Accordingly, the reliability of stored data cannot be assured.
More specifically, if the ultraviolet-shielding layer 403 is damaged, an EEPROM cell is irradiated with ultraviolet rays through this damaged region to damage the stored data. The damage to the ultraviolet-shielding layer 403 can be recognized by externally observing the semiconductor chip having an integrated circuit made up of the EEPROM 402. When, however, the semiconductor chip is incorporated in a data communication device or the like, the state of the EEPROM 402 cannot be always externally observed.
In this case, even if the ultraviolet-shielding layer is damaged, and thus the data is damaged, this state cannot be detected, and information processing is performed using abnormal data.
Since the ultraviolet-shielding layer 403 is formed on a word line or the like, the damage to the ultraviolet-shielding layer 403 may lead to damage or disconnection of an upper wiring layer constituting the EEPROM 402. Also in this case, the damage cannot be detected, and the device may malfunction owing to a defective semiconductor chip.